1. Field of the Invention
The invention relates to a semiconductor process, and in particular to a method and a structure for manufacturing high-resistance polysilicon loads in the semiconductor process.
2. Description of the Related Art
As is well known, high-resistance polysilicon layers are commonly used as loads in 4T SRAM memory cells. Traditionally, to manufacture polysilicon loads, a polysilicon layer is first deposited. Then, a high-energy ion implantation is performed to adjust the resistance thereof. After that, the polysilicon layer is patterned to form a plurality of polysilicon loads by photolithography and etching techniques. Next, parts of the polysilicon loads are ion implanted with a high-concentration dopant, thereby forming the required connectors. Referring to FIG. 1, a structure of polysilicon loads manufactured by the prior art is shown. In FIG. 1, reference numerals 10, 11, 12, 19' and 20 represent a substrate, polysilicon layers, a TEOS layer, polysilicon loads and connectors, respectively. The FIG. 2 is a top view of FIG. 1. In other words, the FIG. 1 is a cross-sectional view of FIG. 2 along line I--I. Clearly, the resistance of the polysilicon loads depends on the amount of the first implanted dopant, the thicknesses, widths and lengths of the polysilicon loads etc. In order to obtain sufficient high-resistance loads, a traditional method is used to reduce the thicknesses, increase the lengths or decrease the widths of polysilicon loads. However, with miniaturization of memory cells, this traditional method can no longer produce polysilicon loads of sufficient high-resistance. The reason is that out-diffusion caused by dopant inside the connectors greatly shortens the effective lengths of such polysilicon loads. In the past, increasing the lengths of polysilicon loads has been limited by the miniaturization of memory cells. Reducing the widths of polysilicon loads has been limited by processing capabilities. Therefore, the drawbacks of the traditional method of manufacturing polysilicon loads has been one of the factors to affect the miniaturization of memories.